The present invention relates to bulk FinFET devices and, more particularly, relates to bulk FinFET devices having uniform high concentration well doping to block the electrical path between the source and drain and minimize the junction leakage current.
In contrast to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETS), which are fabricated using conventional lithographic fabrication methods, nonplanar FETs (Field-Effect Transistors) incorporate various vertical transistor structures, and typically include two or more gate structures formed in parallel. One such semiconductor structure is the “FinFET” which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels.
More particularly, a FinFET device generally includes one or more parallel silicon fin structures (or simply “fins”). The fins extend between a common source electrode and a common drain electrode. A conductive gate structure “wraps around” three sides of the fins, and may be separated from the fins by a standard gate insulator layer. Fins may be suitably doped to produce the desired FET polarity, as is known in the art, such that a gate channel is formed within the fins adjacent to the gate insulator.
Fin structures (and thus FinFET devices) may be formed on a semiconductor substrate. The semiconductor substrate may be a silicon on insulator (SOI) wafer. The silicon on insulator (SOI) wafer comprises a silicon-comprising material layer overlying a silicon oxide layer. Fin structures are formed from the silicon-comprising material layer. The SOI wafer is supported by a support substrate which may also be silicon or another semiconducting material.
Alternatively, the semiconductor substrate may be a bulk silicon wafer from which the fin structures are formed. The bulk silicon wafer comprises a monolithic block of single crystal silicon. A FinFET device formed from a bulk silicon wafer is referred to herein as a “bulk FinFET device”.
Electrical isolation between adjacent fins and between the source and drain electrodes of unrelated FinFET devices is needed. “Unrelated” as used herein means that the devices are not intended to be coupled together. Electrical current leakage is a parasitic effect, which degrades performance of an integrated circuit.